The oscillator circuit is one of the circuits which are most widely used in integrated circuits (IC). In recent years, it is desired to generate a signal with a precious oscillation frequency in the stream of high functionalization in the integrated circuit. Therefore, limiting oscillation frequency jitter is an important goal.
One of the factors of generation of the oscillation frequency jitter is power noise. As one technique to restrain generation of the oscillation frequency jitter by the power noise, a technique is known in which an LDO (low dropout regulator) is disposed between the power and an oscillator. For example, such a technique is disclosed in JP 2015-181238A.
FIG. 1 is a circuit diagram illustrating an example of configuration of an oscillator circuit in which the LDO is disposed between the power and the oscillator. An oscillator circuit 100 of FIG. 1 has an oscillator 101 and an LDO 102. The LDO 102 is disposed between a power terminal 101a of the oscillator 101 and a power supply line 103 to which a power supply voltage IOVCC is supplied, to supply the oscillator power supply voltage VDDOSC to the power terminal 101a of the oscillator 101. The LDO 102 has a PMOS transistor 104 and a differential amplifier 105. The PMOS transistor 104 has a source connected with the power supply line 103, and a drain connected with the power terminal 101a of the oscillator 101. The differential amplifier 105 has a non-inverting input (+) connected with the power terminal 101a of the oscillator 101, and an inverting input (−) connected with a reference voltage generation circuit 106. The reference voltage VREF is supplied to the inversion input of the differential amplifier 105 from the reference voltage generation circuit 106. The differential amplifier 105 controls the gate voltage of the PMOS transistor 104 according to a difference between the oscillator power supply voltage VDDOSC and the reference voltage VREF.
The oscillator circuit 100 having the configuration of FIG. 1, in which the LDO 102 effectively suppresses propagation of power noise from the power supply line 103 to the oscillator 101, effectively suppresses the oscillation frequency jitter.
According to a study by the inventor, however, there is room in improvement in restraint of the oscillation frequency jitter with respect to the oscillator circuit 100 of FIG. 1.